1. Field of the Invention
The field of the invention is programmable controllers, including those controllers which are integrated into numerical control systems as programmable interfaces.
2. Description of the Prior Art
In programmable controllers and interfaces a control program is executed by a processor to read input status data from sensing devices on a machine and to generate output status data to output devices controlling the machine. The processor is coupled to a random access read/write memory (RAM) in which the user control program and the input/output status data are stored. The user loads the control program into the RAM through a program loader or program panel, the latter usually having a keyboard and some form of visual display.
The user control program includes instructions that are widely recognized in the industry by their mnemonic labels, such as XIC, XIO and OTE. These instructions perform common control functions that have become well defined as the art has developed. The user control instructions are converted into binary form by the program panel and then loaded into the main memory. The manner in which these binary-coded program instructions are executed depends upon the architecture of the particular controller.
In Kiffmeyer, U.S. Pat. No. 3,810,118, issued May 7, 1974, the control program instructions are stored in a read-only memory (ROM) and are read and executed in sequence. The instructions have a two-bit operation code and a six-bit operand address. The instructions are simply applied to hardware logic circuits to perform control operations on one-bit operands.
In a much larger controller in Dummermuth, U.S. Pat. No. 3,942,158, issued Mar. 2, 1976, the set of control program instructions is greatly expanded, and operands are stored in memory as sixteen-bit words. The much larger programmable controller in the Dummermuth patent executes three types of controller instructions: bit-oriented instructions, control instructions and word-oriented instructions. The bit-oriented instructions include a four-bit operation code, a four-bit bit pointer code and an operand address.
The processor in this controller is comprised of discrete components that decode and execute the various types of program instructions. Bit-pointer codes are decoded by logic circuitry to isolate individual bits in operands for manipulation. Operation codes are also decoded by logic circuitry to perform the directed operations on selected bits.
With the arrival of microprocessor-based controllers, such as that disclosed in Dummermuth et al, U.S. Pat. No. 4,165,534, issued Aug. 21, 1979, it has become possible to eliminate hardwired logic circuits in favor of program instructions to be executed by the microprocessor. This basic software for hardware trade-off has reduced costs in a field where such trade-offs are not automatically economical.
Microprocessors are directed by machine instructions that have been developed by the manufacturer of the particular chip. Controller-type instructions must therefore be converted to machine instructions before being executed by the microprocessor. In the Dummermuth et al U.S. Pat. No. 4,165,534, this is accomplished by designating the controller-type instructions as macro-instructions that are coupled to groups of machine instructions organized in macro-instruction interpreter routines. While some of the controller-type instructions in this prior controller are completely interpreted by machine instructions, a Boolean processor provides hardware assistance in executing bit-oriented instructions.
The Boolean processor decodes both the operation code and the bit pointer code in each bit-oriented program instruction, and performs the directed operation on a selected bit in an operand. To perform the bit-pointer decoding with machine instructions in the controller of the Dummermuth et al U.S. Pat. No. 4,165,534, would have required additional processing time for each bit-oriented program instruction and would have added substantially to the overall processing time for the control program.
It is standard practice in programmable controllers to check data, including program instructions, for parity errors. Memories using currently available circuit chips experience "soft" parity errors due to alpha radiation in the environment. A malfunctioning memory cell can return to normal operation so that the location of the error cannot be found by the time diagnostic routines are applied to the controller processor. These errors are in contrast to "hard" errors, where a memory cell has undoubtedly failed and the affected memory chip must be replaced. The controllers of the prior art do not effectively detect both types of errors, and could be more expensive to maintain and troubleshoot as a result.
The development of prior controllers included the development of a program panel designed especially for operation with the processor of that particular controller. Recent advances in the microcomputer art have provided an opportunity to greatly increase the capabilities of controller processors relative to their cost. There is not, however, a corresponding advantage to be realized from redesigning system program panels. In fact, it would be desirable from a customer viewpoint to be able to use an existing program panel with newly developed central processor units. A technical problem has been the adaptation of a processor in a newly developed programmable interface to an existing program panel for a programmable controller.
More specifically, such a processor must be able to translate from one set of macro-instruction operation codes and bit-pointer codes to another before the macro-instruction operation codes and bit-pointer codes are coupled to an interpreter routine. This problem can be more complex where the operation codes and bit pointer codes in two different controllers have different numbers of bits, and it is desired to use common peripheral equipment, such as a program panel, with both controllers. It would be possible to program a new controller to translate one set of codes received from a program panel to another set of codes which it would then recognize and execute. This would require added memory space and substantial processing time. To provide an economical programmable controller it is necessary to efficiently allocate functions between a processor operable with machine language instructions and other hardware in a central processor unit.